The Ridiculously Nerdy Intel Bet That Could Rake in Billions

It’s inactive an highly challenging proposition. “Packaging is not arsenic casual arsenic saying, ‘I privation to tally 100,000 wafers per month,’” says Jim McGregor, a longtime spot manufacture expert and the laminitis of Tirias Research, referring to a continuous travel of chips successful assorted stages of production. “It truly comes down to whether Intel’s [packaging] fabs tin marque deals. If we spot them expanding those operations more, that’s an indicator that they have.”

Last month, Anwar Ibrahim, the premier curate of Malaysia, revealed successful a station connected Facebook that Intel is expanding its Malaysian chip-making facilities, which were archetypal established backmost successful the 1970s. Ibrahim said the caput of Intel’s Foundry, Naga Chandrasekaran, had “outlined plans to commence the archetypal phase” of expansion, which would see precocious packaging.

“I invited Intel's determination to statesman operations for the analyzable aboriginal this year,” a translated mentation of Ibrahim’s station read. An Intel spokesperson, John Hipsher, confirmed that it’s gathering retired further spot assembly and trial capableness successful Penang, “amid rising planetary request for Intel Foundry packaging solutions.”

Package Store

According to Chandrasekaran, who took implicit Intel’s Foundry operations successful 2025 and spoke exclusively with WIRED during the reporting of this story, the word “advanced packaging” itself didn’t beryllium a decennary ago.

Chips person ever required immoderate benignant of integration of transistors and capacitors, which power and store energy. For a agelong clip the semiconductor manufacture was focused connected miniaturization, or, shrinking the size of components connected chips. As the satellite began demanding much from its computers successful the 2010s, chips started to get adjacent much dense with processing units, high-bandwidth memory, and each of the indispensable connective parts. Eventually, chipmakers started to instrumentality a system-in-packages oregon package-on-package approach, successful which aggregate components were stacked connected apical of 1 different successful bid to compression much powerfulness and representation retired of the aforesaid aboveground space. 2D stacking gave mode to 3D stacking.

TSMC, the world’s starring semiconductor manufacturer, began offering packaging technologies similar CoWoS (chip connected wafer connected substrate) and, later, SoIC (system connected integrated chip) to customers. Essentially, the transportation was that TSMC would grip not conscionable the beforehand extremity of chip-making—the wafer part—but besides the backmost end, wherever each of the spot tech would beryllium packaged together.

Intel had ceded its spot manufacturing pb to TSMC astatine this point, but continued to put successful packaging. In 2017 it introduced a process called EMIB, oregon embedded multi-die interconnect bridge, which was unsocial due to the fact that it shrunk the existent connections, oregon bridges, betwixt the components successful the spot package. In 2019, it introduced Foveros, an precocious die-stacking process. The company’s adjacent packaging advancement was a bigger leap: EMIB-T.

Announced past May, EMIB-T promises to amended powerfulness ratio and awesome integrity betwixt each the components connected the chips. One erstwhile Intel worker with nonstop cognition of the company’s packaging efforts tells WIRED that Intel’s EMIB and EMIB-T are designed to beryllium a much “surgical” mode of packaging chips than TSMC’s approach. Like astir spot advancements, this is expected to beryllium much powerfulness efficient, prevention space, and, ideally, prevention customers wealth successful the agelong runThe institution says EMIB-T volition rotation retired successful fabs this year.